FPGA. Verilog VHDL课程

VHDL.代码

按下按钮时 FPGA.，有不可预测的反弹是不必要的。此VHDL代码是 去抖动按钮 在FPGA上仅在FPGA上的按钮被按下时，仅通过输入时钟的单个脉冲产生单个脉冲，保持足够长，并释放。 上次，我介绍了一个简单的Verilog代码。

这 VHDL.项目 是出现一个 VHDL. 代码。提供完整的VHDL代码和测试台。

VHDL.代码

VHDL.代码：

--fpga4student.com: FPGA. projects, Verilog projects, VHDL.项目
-- VHDL project: VHDL代码
-- Generate Slow clock enable for debouncing buttons 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
实体 Clock_Enable._debouncing_button is
port(
 clk: in std_logic; -- input clock on FPGA 100Mhz
                           -- Change counter threshold accordingly
 slow_clk_enable: out std_logic）; 
结尾 Clock_Enable._debouncing_button;
architecture 行为的 of Clock_Enable._debouncing_button is
signal counter: std_logic_vector(27 downto 0):=(others => '0'）; 
begin
process(clk)
begin
if(rising_edge(clk)) then
  counter <= counter + x"0000001"; 
  if(counter>=x"003D08F") then -- reduce this number for simulation
   counter <=  (others => '0'）; 
  结尾 if;
 结尾 if;
结尾 process;
 slow_clk_enable <= '1' when counter=x"003D08F" else '0'; -- reduce this number for simulation
结尾 行为的;
--fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL代码
-- VHDL D-flip-flop with clock enable signal for debouncing buttons 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
实体 DFF_Debouncing_Button is
port(
 clk: in std_logic;
 clock_enable: in std_logic;
 D: in std_logic;
 Q: out std_logic:='0'）; 
结尾 DFF_Debouncing_Button;
architecture 行为的 of DFF_Debouncing_Button is
begin
process(clk)
begin
 if(rising_edge(clk)) then
  if(clock_enable='1') then
   Q <= D;
  结尾 if;
 结尾 if;
结尾 process;
结尾 行为的;
--fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL代码
-- VHDL code for button debouncing on FPGA 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
实体 Debouncing_Button_VHDL is
port(
 button: in std_logic;
 clk: in std_logic;
 debounced_button: out std_logic）; 
结尾 Debouncing_Button_VHDL;
architecture 行为的 of Debouncing_Button_VHDL is
signal slow_clk_enable: std_logic;
signal Q1,Q2,Q2_bar,Q0: std_logic;
begin

clock_enable_generator: 实体 工作.clock_enable_debouncing_button 港口 地图 
      ( clk => clk,
        slow_clk_enable => slow_clk_enable
      );
Debouncing_FF0: 实体 工作.dff_debouncing_button. 港口 地图 
      ( clk => clk,
        clock_enable => slow_clk_enable,
        D => button,
        Q => Q0
      ); 
debouncing_ff1.: 实体 工作.dff_debouncing_button. 港口 地图 
      ( clk => clk,
        clock_enable => slow_clk_enable,
        D => Q0,
        Q => Q1
      );      
Debouncing_FF2: 实体 工作.dff_debouncing_button. 港口 地图 
      ( clk => clk,
        clock_enable => slow_clk_enable,
        D => Q1,
        Q => Q2
      ); 
 Q2_bar <= 不是 Q2;
 debounced_button <= Q1 和 Q2_bar;
结尾 行为的;

testbench vhdl代码 在FPGA上的脱扣按钮:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL code for button debouncing on FPGA 
-- testbench vhdl代码 button debouncing
ENTITY tb_debouncing_button_VHDL IS
END tb_debouncing_button_VHDL;
 
ARCHITECTURE behavior OF tb_debouncing_button_VHDL IS
    -- Component Declaration for VHDL code for button debouncing
    COMPONENT Debouncing_Button_VHDL
    港口(
         button : IN  std_logic;
         clk : IN  std_logic;
         debounced_button : OUT  std_logic
        );
    END COMPONENT;
   signal button : std_logic := '0';
   signal clk : std_logic := '0';
   signal debounced_button. : std_logic;
   constant clk_period : time := 10 ns;
BEGIN
 -- Instantiate VHDL code for button debouncing
   uut: Debouncing_Button_VHDL 港口 地图 (
          button => button,
          clk => clk,
          debounced_button => debounced_button
        );
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period;
  clk <= '1';
  wait for clk_period;
   结尾 process;
   -- Stimulus process
   stim_proc: process
   begin  
      -- hold reset state for 100 ns.
      wait for 100 ns; 

      wait for clk_period*10;
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 20 ns; 
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 30 ns; 
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 40 ns; 
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 30 ns;  
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 1000 ns;  
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 20 ns; 
  button <= '0';
  wait for 10 ns; 
  button <= '1';
  wait for 30 ns; 
  button <= '0';
      wait;
   结尾 process;

END;

VHDL.代码的模拟波形：

VHDL.代码

仅在按下输入按钮时，仅在上面的模拟波形中显示单个脉冲，保持足够长，并释放。 

FPGA. Verilog VHDL课程

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