与测试台的计数器的Verilog代码

在这个项目中, verilog.code 为了 柜台试验台 将呈现,包括计数器,下计数器,上下计数器和随机计数器。

与测试台的计数器的Verilog代码

verilog.code for up counter:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, verilog.projects, VHDL projects
// Verilog代码为柜台
module up_counter(input clk, reset, output[3:0] counter
    );
reg [3:0] counter_up;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_up <= 4'd0;
else
 counter_up <= counter_up + 4'd1;
end 
assign counter = counter_up;
endmodule

Verilog测试票代码柜台:


// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// Verilog代码为柜台 with testbench
// Testbench Verilog代码为柜台
module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;

up_counter dut(clk, reset, counter);
initial begin 
clk=0;
为了ever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule 

仿真波形用于柜台:

verilog.code for up counter

verilog.code for down counter:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// 击落柜台的Verilog代码
module down_counter(input clk, reset, output [3:0] counter
    );
reg [3:0] counter_down;

// down counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_down <= 4'hf;
else
 counter_down <= counter_down - 4'd1;
end 
assign counter = counter_down;
endmodule

verilog.Testbench码下计数器:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// 击落柜台的Verilog代码 with testbench
// Testbench 击落柜台的Verilog代码
module downcounter_testbench();
reg clk, reset;
wire [3:0] counter;

down_counter dut(clk, reset, counter);
initial begin 
clk=0;
为了ever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule 

仿真波形下计数器:

verilog.code for down counter

verilog. 上下计数器的代码:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// 上下计数器的Verilog代码
module up_down_counter(input clk, reset,up_down, output[3:0]  counter
    );
reg [3:0] counter_up_down;

// down counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_up_down <= 4'h0;
else if(~up_down)
 counter_up_down <= counter_up_down + 4'd1;
else
 counter_up_down <= counter_up_down - 4'd1;
end 
assign counter = counter_up_down;
endmodule

Verilog测试票代码上下计数器:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// 上下计数器的Verilog代码 with testbench
// Testbench 上下计数器的Verilog代码
module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;

up_down_counter dut(clk, reset,up_down, counter);
initial begin 
clk=0;
为了ever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule 

上下计数器的仿真波形:

verilog.code for up-down counter

Verilog代码随机计数器使用LFSR:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// Verilog code for random counter using linear shift feedback register
 module random_counter_lfsr(input clk, rst_n,   
                 input[4:0] initialized_value,  
                 output[4:0] counter_random);  
 wire [4:0] counter_lfsr;  
 wire d_xor;  
  xor xor_u(d_xor,counter_lfsr[1],counter_lfsr[4]);  
 D_FF u0(.q(counter_lfsr[0]), .d(counter_lfsr[4]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[0]));  
 D_FF u1(.q(counter_lfsr[1]), .d(counter_lfsr[0]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[1]));  
 D_FF u2(.q(counter_lfsr[2]), .d(d_xor), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[2]));  
 D_FF u3(.q(counter_lfsr[3]), .d(counter_lfsr[2]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[3]));  
 D_FF u4(.q(counter_lfsr[4]), .d(counter_lfsr[3]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[4])); 
 assign counter_random = counter_lfsr;  
 endmodule    
 // FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// Verilog code for random counter using linear shift feedback register
// Verilog code for D_FF using in random counter
 module D_FF (q, d, rst_n, clk,init_value);  
 output q;  
 input d, rst_n, clk,init_value;  
 reg q; 
 always @(posedge clk or negedge rst_n)  
 if (~rst_n)  
 q <= init_value;    
 else  
 q <= d; 
 endmodule  

Verilog使用LFSR的随机计数器测试票代码:

// FPGA projects using Verilog/ VHDL
// yl315.net: FPGA projects, Verilog projects, VHDL projects
// Verilog code for random counter with testbench
// Testbench Verilog code for random counter
module randomcounter_testbench();
reg clk, reset;
reg [4:0] initialized_value;
wire [4:0] counter_random;

random_counter_lfsr dut( clk, reset,   
                 initialized_value,  
                 counter_random);  
initial begin 
clk=0;
为了ever #5 clk=~clk;
end
initial begin
reset=0;
initialized_value=5'b11111;
#20;
reset=1;
end
endmodule 

随机计数器模拟波形:

Verilog代码用于随机计数器使用LFSR

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