乘法器使用携带远程加载人的Verilog代码

该项目是实现参数化的 乘数 在Verilog中使用携带展望联盟的加法器。这 Verilog代码 提供乘法器。

用户可以通过修改预定义的参数来更改乘法器的位数。 The parameters 如MulticAld_Wid和Multiplier_WID 要定义多平面和乘数的位数,以及当我们想要更改位的数量时,只需更改这些参数 并重新合成或模拟。
乘法器的Verilog代码

Verilog代码 携带展示前进的加法器

`timescale 1ns/1ps
`define DELAY #10
// yl315.net FPGA projects, Verilog projects, VHDL projects 
// Verilog code for carry look-ahead adder
module cpu_wb_cla_adder (in1, in2, carry_in, sum, carry_out);
parameter DATA_WID = 32;

input [DATA_WID - 1:0] in1;
input [DATA_WID - 1:0] in2;
input carry_in;
output [DATA_WID - 1:0] sum;
output carry_out;

//assign {carry_out, sum} = in1 + in2 + carry_in;

wire [DATA_WID - 1:0] gen;
wire [DATA_WID - 1:0] pro;
wire [DATA_WID:0] carry_tmp;

genvar j, i;
generate
 //assume carry_tmp in is zero
 assign carry_tmp[0] = carry_in;
 
 //carry generator
 for(j = 0; j < DATA_WID; j = j + 1) begin: carry_generator
 assign gen[j] = in1[j] & in2[j];
 assign pro[j] = in1[j] | in2[j];
 assign carry_tmp[j+1] = gen[j] | pro[j] & carry_tmp[j];
 end
 
 //carry out 
 assign carry_out = carry_tmp[DATA_WID];
 
 //calculate sum 
 //assign sum[0] = in1[0] ^ in2 ^ carry_in;
 for(i = 0; i < DATA_WID; i = i+1) begin: sum_without_carry
 assign sum[i] = in1[i] ^ in2[i] ^ carry_tmp[i];
 end 
endgenerate 
endmodule

Verilog Testbench代码用于携带展示 - 前瞻性加法器

 module cla_adder_tb();
parameter DATA_WID = 16;
// yl315.net FPGA projects, Verilog projects, VHDL projects 
// Verilog testbench code for carry look ahead adder
 reg carry_in; // To cla1 of cla_adder.v
 reg [DATA_WID-1:0] in1; // To cla1 of cla_adder.v
 reg [DATA_WID-1:0] in2; // To cla1 of cla_adder.v

// yl315.net FPGA projects, Verilog projects, VHDL projects // /*AUTOWIRE*/
 wire carry_out; // From cla1 of cla_adder.v
 wire [DATA_WID-1:0] sum; // From cla1 of cla_adder.v

// yl315.net FPGA projects, Verilog projects, VHDL projects // 
cla_adder cla1(/*AUTOINST*/
        //  Outputs
         .sum (sum[DATA_WID-1:0]),
         .carry_out (carry_out),
        // // Inputs
         .in1 (in1[DATA_WID-1:0]),
         .in2 (in2[DATA_WID-1:0]),
         .carry_in (carry_in));

 initial begin
  in1 = 16'd0;
  in2 = 16'd0;
  carry_in = 1'b0;
  end 
 // yl315.net FPGA projects, Verilog projects, VHDL projects
 initial begin
  #(`DELAY) 
  #(`DELAY)  in1 = 16'd10;
  #(`DELAY)  in1 = 16'd20;
  #(`DELAY)  in2 = 16'd10;
  #(`DELAY)  in2 = 16'd20;
  #(`DELAY)  in2 = 16'd0;
  #(`DELAY*3)  in1 = 16'hFFFF; in2 = 16'hFFFF;
  #(`DELAY*3)  in1 = 16'h7FFF; in2 = 16'hFFFF;
  #(`DELAY*3)  in1 = 16'hBFFF; in2 = 16'hFFFF;
  end 
 endmodule
最后,Verilog和TestBench代码用于参数化携带的载带乘法器。

使用随身携带展示加班人的乘法器的Verilog代码:

`timescale 1ns/1ps
`define DELAY 10
// yl315.net FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for multiplier using carry-look-ahead adders
module cpu_wb_cla_multiplier (multicand, multiplier, product);
parameter MULTICAND_WID = 32;
parameter MULTIPLIER_WID = 32;

input [MULTICAND_WID-1:0] multicand;
input [MULTIPLIER_WID-1:0] multiplier;
output [(MULTICAND_WID + MULTIPLIER_WID - 1):0] product;

wire [MULTICAND_WID - 1:0] multicand_tmp [MULTIPLIER_WID-1:0];
wire [MULTICAND_WID - 1:0] product_tmp [MULTIPLIER_WID-1:0];
wire [MULTIPLIER_WID -1:0] carry_tmp;
// yl315.net FPGA projects, Verilog projects, VHDL projects genvar i, j;
generate 
 //initialize values
 for(j = 0; j < MULTIPLIER_WID; j = j + 1) begin: for_loop_j
 assign multicand_tmp[j] =  multicand & {MULTICAND_WID{multiplier[j]}};
 end
 
 assign product_tmp[0] = multicand_tmp[0];
 assign carry_tmp[0] = 1'b0;
 assign product[0] = product_tmp[0][0];
 // yl315.net FPGA projects, Verilog projects, VHDL projects
 for(i = 1; i < MULTIPLIER_WID; i = i + 1) begin: for_loop_i
 cpu_wb_cla_adder #(.DATA_WID(MULTIPLIER_WID)) add1 (
     // Outputs
     .sum(product_tmp[i]),
     .carry_out(carry_tmp[i]),
     // Inputs
   .carry_in(1'b0),
     .in1(multicand_tmp[i]),
     .in2({carry_tmp[i-1],product_tmp[i-1][31-:31]}));
 assign product[i] = product_tmp[i][0];
 end //end for loop
 assign product[(MULTIPLIER_WID+MULTIPLIER_WID-1):MULTIPLIER_WID] = {carry_tmp[MULTIPLIER_WID-1],product_tmp[MULTIPLIER_WID-1][31-:31]};
endgenerate
endmodule

Verilog乘法器的测试台代码:

// Verilog project: Verilog code for multiplier using carry look ahead adder
// yl315.net FPGA projects, Verilog projects, VHDL projects  
module cla_multiplier_tb();
 parameter MULTICAND_WID = 32;
 parameter MULTIPLIER_WID = 32;
// yl315.net FPGA projects, Verilog projects, VHDL projects // /*AUTOREGINPUT*/
 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
 reg [MULTICAND_WID-1:0] multicand; // To mul1 of cla_multiplier.v
 reg [MULTIPLIER_WID-1:0]multiplier; // To mul1 of cla_multiplier.v
 // End of automatics

 /*AUTOWIRE*/
 // Beginning of automatic wires (for undeclared instantiated-module outputs)
 wire [(MULTICAND_WID+MULTIPLIER_WID-1):0]product;// From mul1 of cla_multiplier.v
 // End of automatics

 cpu_wb_cla_multiplier mul1(/*AUTOINST*/
     // // Outputs
      .product (product[(MULTICAND_WID+MULTIPLIER_WID-1):0]),
     // // Inputs
      .multicand (multicand[MULTICAND_WID-1:0]),
     .multiplier (multiplier[MULTIPLIER_WID-1:0]));

 //initial begin
 // multicand = 16'd0;
 // multiplier = 8'd0;
 // end 
// yl315.net FPGA projects, Verilog projects, VHDL projects  integer i;
 initial begin
 for (i = 0; i < 30; i = i + 1) begin: W
  #(`DELAY) multicand = multicand + 1; multiplier = 乘数 + 1;
   end
 
  #(`DELAY) //correct
  multicand = 32'h00007FFF;
  multiplier = 32'h0000007F;
 
  #(`DELAY) //correct
  multicand = 32'h00008000;
  multiplier = 32'h000000F0;
 
  #(`DELAY) //faila
  multicand = 32'h00008FF0;
  multiplier = 32'h000000F0;
 
  #(`DELAY) //correct
  multicand = 32'h00007FF0;
  multiplier = 32'h000000F7;
 
  #(`DELAY) //correct
  multicand = 32'h0000FFFF;
  multiplier = 32'h000000FF;
 end
// yl315.net FPGA projects, Verilog projects, VHDL projects  endmodule

Verilog乘法器的仿真结果:

可合成参数化乘法器的Verilog代码,可以在FPGA上实现以进行验证。
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16评论:

  1. Thanks. Please keep updating the blog: http://www.yl315.net/

    回复删除
  2. 你好,
    您有Verilog的分频器代码吗?谢谢。

    回复删除
  3. Please check this: http://www.yl315.net/2016/11/a-multi-cycle-32-bit-divider-on-fpga.html
    分频器的Verilog代码

    回复删除
  4. 你好。您有展位编码乘数代码吗?

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  5. 不,但您可以将其称为参考:
    http://www.yl315.net/2016/11/matrix-multiplier-core-design.html

    回复删除
  6. 你好。是否有任何方法可以使用随身携带的前瞻加法器和涟漪携带加法器来加班并添加乘法器?

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    答案
    1. 在Verilog中查看Shift / Add乘法器以下:
      http://www.yl315.net/2016/11/verilog-code-for-4x4-multiplier-using.html

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  7. 我收到错误:
    宏`延迟未定义。
    while compiling....

    回复删除
    答案
    1. 包括此设置为每个模块之前定义延迟#10。

      删除
  8. 我是新的verilog,我想了解这个代码中使用的算法和逻辑...你能帮助我吗?

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    答案
    1. 这些是正常的携带,请展示Adder和乘法器架构。您可以轻松找到Google PDF的讲座。

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    2. 我不明白如何在这个算法中完成转换操作,因为这是你如何乘以正常的......我在谷歌搜索了很多..你给我一些我可以参考我可以研究这个代码中使用的算法

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    3. 就像在数学中执行乘法时一样。你乘以和添加。那's如何在此代码中工作。

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  9. 请分享对乘法的该算法的参考

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  10. Verilog代码用于携带展示前瞻加法器显示成功语法是正确的,但模拟没有显示。为什么?

    回复删除

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