[全fun88英超代码]矩阵乘法设计使用fun88英超

fun88英超. 代码 矩阵乘法 被表达。该fun88英超项目旨在开发和实现可合成的矩阵乘法器核心,其能够对具有32x32大小的矩阵执行矩阵计算。

矩阵的每个组件 是16位无符号整数。核心在Xilinx上实施 FPGA. Spartan-6 XC6SLX45-CSG324-3。完成了行为和路线后验证。与MATLAB实现结果进行准确地进行模拟结果。

   
矩阵乘法的fun88英超代码

设计核心的框图
设计核心基于矩阵的参考设计,其中Xilinx核心发生器生成输入和输出缓冲区以保存输入和输出数据。主要工作是计算的块 矩阵乘法 。基于矩阵乘法理论,矩阵乘法由以下等式完成:

矩阵乘法的fun88英超代码
计算CIJ,在状态“stReadBufferAB”,我们必须读出所有32列行I和32列j的行,并且像等式一样乘法和累积。此外,我们添加一个州“stSaveData”到参考核心的FSM,旨在在进入下一个状态之前保存累积数据“stWriteBufferC”.
矩阵乘法的fun88英超代码
块界面的设计核心

V HDL. 矩阵乘法器的顶级代码:

 -- fpga4student.com  FPGA.  projects, Verilog projects,  fun88英超项目  
 -- fun88英超 project: fun88英超 code for matrix multiplcation
 library ieee;   
 use ieee.std_logic_1164.all;   
 use ieee.numeric_std.all;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- Required entity declaration  
 entity IntMatMulCore is  
      port(  
           Reset, Clock,      WriteEnable, BufferSel:      in std_logic;  
           WriteAddress: in std_logic_vector (9 downto 0);  
           WriteData:           in std_logic_vector (15 downto 0);  
           ReadAddress:      in std_logic_vector (9 downto 0);  
           ReadEnable:      in std_logic;  
           ReadData:           out std_logic_vector (63 downto 0);  
           DataReady:           out std_logic  
      );  
 end IntMatMulCore;  
 architecture IntMatMulCore_arch of IntMatMulCore is  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects 
 COMPONENT dpram1024x16  
  PORT (  
   clka : IN STD_LOGIC;  
   wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);  
   addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);  
   dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  
   clkb : IN STD_LOGIC;  
       enb : IN STD_LOGIC;  
   addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);  
   doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)  
  );  
 END COMPONENT;  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects 
 COMPONENT dpram1024x64  
  PORT (  
   clka : IN STD_LOGIC;  
   wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);  
   addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);  
   dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);  
   clkb : IN STD_LOGIC;  
   enb : IN STD_LOGIC;  
   addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);  
   doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)  
  );  
 END COMPONENT;  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
 type     stateType is (stIdle, stWriteBufferA, stWriteBufferB, stReadBufferAB, stSaveData, stWriteBufferC, stComplete);  
 signal presState: stateType;  
 signal nextState: stateType;  
 signal iReadEnableAB, iCountReset,iCountEnable, iCountEnableAB,iCountResetAB: std_logic;  
 signal iWriteEnableA, iWriteEnableB, iWriteEnableC: std_logic_vector(0 downto 0);  
 signal iReadDataA, iReadDataB: std_logic_vector (15 downto 0);  
 signal iWriteDataC: std_logic_vector (63 downto 0);  
 signal iCount, iReadAddrA, iReadAddrB,iRowA : unsigned(9 downto 0);  
 signal CountAT,CountBT:unsigned(9 downto 0);  
 signal iColB:unsigned(19 downto 0);  
 signal irow,icol,iCountA,iCountB: unsigned(4 downto 0);  
 signal iCountEnableAB_d1,iCountEnableAB_d2,iCountEnableAB_d3: std_logic;  
 begin  
      --Write Enable for RAM A   
      iWriteEnableA(0) <= WriteEnable and BufferSel;  
      --Write Enable for RAM B  
      iWriteEnableB(0) <= WriteEnable and (not BufferSel); 
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects 
      --Input Buffer A Instance  
           InputBufferA : dpram1024x16  
           PORT MAP (  
                clka => Clock,  
                wea  => iWriteEnableA,  
                addra => WriteAddress,  
                dina => WriteData,  
                clkb      => Clock,  
                enb     => iReadEnableAB,  
                addrb => std_logic_vector(iReadAddrA),  
                doutb => iReadDataA  
           );  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      InputBufferB : dpram1024x16  
           PORT MAP (  
                clka => Clock,  
                wea  => iWriteEnableB,  
                addra => WriteAddress,  
                dina => WriteData,  
                clkb      => Clock,  
                enb     => iReadEnableAB,  
                addrb => std_logic_vector(iReadAddrB),  
                doutb => iReadDataB  
           );  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      OutputBufferC : dpram1024x64  
           PORT MAP (  
                clka      => Clock,  
                wea      => iWriteEnableC,  
                addra => std_logic_vector(iCount),  
                dina      => iWriteDataC,  
                clkb      => Clock,  
                enb      => ReadEnable,  
                addrb => ReadAddress,  
                doutb => ReadData  
           );  
      process(Clock,Reset)  
      begin  
      if(rising_edge(Clock)) then  
      if(Reset='1') then  
      iCountEnableAB_d1 <= '0';  
      iCountEnableAB_d2 <= '0';  
      else  
      iCountEnableAB_d1 <= iCountEnable;  
      iCountEnableAB_d2 <= iCountEnableAB_d1;  
      end if;  
      end if;  
      end process;  
      iCountEnableAB_d3 <= (not iCountEnableAB_d2) AND iCountEnableAB_d1 ;  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      process (Clock)  
      begin  
           if rising_edge (Clock) then  
                if(Reset='1') then  
                     iWriteDataC <= (others => '0');  
                elsif(iWriteEnableC(0)='1') then  
                     iWriteDataC <= (others => '0');  
                elsif(iCountEnableAB_d3='1') then  
                     iWriteDataC <= (others => '0');  
                elsif(iReadEnableAB='1') then   
                     iWriteDataC <= iWriteDataC + std_logic_vector(signed(iReadDataA(15)&iReadDataA)*signed(iReadDataB(15)&iReadDataB));       
                end if;   
           end if;   
      end process;  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
       process (Clock)  
      begin  
           if rising_edge (Clock) then  
                if Reset = '1' then  
                     presState <= stIdle;  
                     iCountA <= (others=>'0');  
                     iCountB <= (others=>'0');  
                else  
                     presState <= nextState;  
                     if iCountResetAB = '1' then  
                          iCountA <= (others=>'0');  
                          iCountB <= (others=>'0');  
                     elsif iCountEnableAB = '1' then  
                          iCountA <= iCountA + 1;  
                          iCountB <= iCountB + 1;  
                     end if;  
                end if;  
                if iCountReset = '1' then  
                     iCount <= (others=>'0');  
                elsif iCountEnable = '1' then  
                     iCount <= iCount + 1;  
                end if;  
           end if;  
      end process;  
      iRowA <= iCount srl 5;  
      iColB <= ("0000000000"&iCount) - iRowA*32;  
      irow <= iRowA(4 downto 0);  
      icol <= iColB(4 downto 0);  
      CountAT <= "00000"&iCountA;  
      CountBT <= "00000"&iCountB;  
      iReadAddrA <= (iRowA sll 5)+CountAT;  
      iReadAddrB <= (CountBT sll 5)+ iColB(9 downto 0);  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      process (presState, WriteEnable, BufferSel, iCount, iCountA, iCountB)  
      begin  
           -- signal defaults  
           iCountResetAB <= '0';  
           iCountReset <= '0';  
           iCountEnable <= '1';  
           iReadEnableAB <= '0';   
           iWriteEnableC(0) <= '0';  
           Dataready <= '0';  
           iCountEnableAB <= '0';  
           case presState is  
                when stIdle =>       
                     if (WriteEnable = '1' and BufferSel = '1') then  
                          nextState <= stWriteBufferA;  
                     else  
                          iCountReset <= '1';  
                          nextState <= stIdle;  
                     end if;  
                when stWriteBufferA =>  
                     if iCount = x"3FF" then  
                          report "Writing A";  
                          iCountReset <= '1';                      
                          nextState <= stWriteBufferB;  
                      else  
                          nextState <= stWriteBufferA;  
                     end if;  
                when stWriteBufferB =>  
                     report "Writing B";  
                     if iCount = x"3FF" then  
                          iCountReset <= '1';                      
                          nextState <= stReadBufferAB;  
                      else  
                          nextState <= stWriteBufferB;  
                     end if;  
                when Streadbufferab. =>  
                     iReadEnableAB <= '1';  
                     iCountEnable <= '0';  
                     report "CalculatingAB";  
                     if iCountA = x"1F" and iCountB = x"1F" then  
                          nextState <= stSaveData;  
                          report "Calculating";  
                          iCountEnableAB <= '0';  
                          iCountResetAB <= '1';  
                     else  
                          nextState <= stReadBufferAB;  
                          iCountEnableAB <= '1';  
                          iCountResetAB <= '0';  
                     end if;  
                when Stsavedata. =>   
                     iReadEnableAB <= '1';  
                     iCountEnable <= '0';  
                     nextState <= stWriteBufferC;  
                when stwritebuffac. =>  
                     iWriteEnableC(0) <= '1';  
                     report "finish 1 component";  
                     if iCount = x"3FF" then  
                          iCountReset <= '1';                           
                          nextState <= stComplete;  
                      else  
                          nextState <= stReadBufferAB;  
                     end if;                 
                when stComplete =>  
                     DataReady <= '1';  
                     nextState <= stIdle;                      
           end case;  
      end process;  
 end IntMatMulCore_arch;

下面是要从文本文件读取矩阵的测试代码,并将结果写入输出文本文件:

-- fun88英超 project: 矩阵乘法的fun88英超代码
-- fpga4student.com  FPGA.  projects, Verilog projects, fun88英超 projects   
-- Testbench 矩阵乘法的fun88英超代码
 library ieee;  
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_textio.all;  
 use ieee.numeric_std.all;  
 use std.textio.all;  
 entity tb_IntMatMultCore is  
 end tb_IntMatMultCore;  
 architecture behavior of tb_IntMatMultCore is   
 component IntMatMulCore  
      port(  
           Reset, Clock,      WriteEnable, BufferSel:      in std_logic;  
           WriteAddress: in std_logic_vector (9 downto 0);  
           WriteData:           in std_logic_vector (15 downto 0);  
           ReadAddress:      in std_logic_vector (9 downto 0);  
           ReadEnable:      in std_logic;  
           ReadData:           out std_logic_vector (63 downto 0);  
           DataReady:           out std_logic  
      );  
 end component;        
 signal tb_Reset : std_logic := '0';  
 signal tb_Clock : std_logic := '0';  
 signal tb_BufferSel : std_logic := '0';  
 signal tb_WriteEnable : std_logic := '0';  
 signal tb_WriteAddress : std_logic_vector(9 downto 0) := (others => '0');  
 signal tb_WriteData : std_logic_vector(15 downto 0) := (others => '0');  
 signal tb_ReadEnable : std_logic := '0';  
 signal tb_ReadAddress : std_logic_vector(9 downto 0) := (others => '0');  
 signal tb_DataReady : std_logic;  
 signal tb_ReadData : std_logic_vector(63 downto 0);  
 -- Clock period definitions  
 constant period : time := 100 ns;    
 begin  
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      -- Instantiate the Unit Under Test (UUT)  
      uut: IntMatMulCore   
           PORT MAP (  
                Reset                    => tb_Reset,  
                Clock                    => tb_Clock,  
                WriteEnable          => tb_WriteEnable,  
                BufferSel          => tb_BufferSel,  
                WriteAddress     => tb_WriteAddress,  
                WriteData          => tb_WriteData,            
                ReadEnable          => tb_ReadEnable,  
                ReadAddress          => tb_ReadAddress,  
                ReadData               => tb_ReadData,  
                DataReady          => tb_DataReady  
    );  
  -- Test Bench Statements  
      process is       
      begin  
           --while now <= 10000000000000 * period loop  
                tb_Clock <= '0';  
                wait for period/2;  
                tb_Clock <= '1';  
                wait for period/2;  
           --end loop;  
           --wait;  
      end process;  
      process is       
      begin  
           tb_Reset <= '1';  
           wait for 10*period;  
           tb_Reset <= '0';  
           wait;    
      end process;  
      writingA: process is                                
           file FIA: TEXT open READ_MODE is "InputA.txt";  -- the input file must have 17 rows  
           file FIB: TEXT open READ_MODE is "InputB.txt";  -- the input file must have 17 rows  
           variable L: LINE;  
           variable tb_MatrixData: std_logic_vector(15 downto 0);  
      begin  
           tb_WriteEnable <= '0';  
           tb_BufferSel <= '1';  
           tb_WriteAddress <= "11"&x"FF";  
           wait for 20*period;  
           READLINE(FIA, L);  
           while not ENDFILE(FIA) loop  
                READLINE(FIA, L);            
                HREAD(L, tb_MatrixData);       
                wait until falling_edge(tb_Clock);  
                tb_WriteAddress <= std_logic_vector(unsigned(tb_WriteAddress)+1);  
                tb_BufferSel <= '1';  
                tb_WriteEnable <= '1';  
                tb_WriteData <=tb_MatrixData;  
           end loop;  
           READLINE(FIB, L);  
           while not ENDFILE(FIB) loop  
                READLINE(FIB, L);            
                HREAD(L, tb_MatrixData);       
                wait until falling_edge(tb_Clock);  
                tb_WriteAddress <= std_logic_vector(unsigned(tb_WriteAddress)+1);  
                tb_BufferSel <= '0';  
                tb_WriteEnable <= '1';  
                tb_WriteData <=tb_MatrixData;  
           end loop;  
           wait for period;  
           tb_WriteEnable <= '0';            
           wait;   
      end process;       
 -- fpga4student.com FPGA projects, Verilog projects, fun88英超 projects
      reading: process is                                
           file FO: TEXT open WRITE_MODE is "outputmultc.txt.";  
           file FI: TEXT open READ_MODE is "OutputMultC_matlab.txt";  
           variable L, Lm: LINE;  
           variable v_ReadDatam: std_logic_vector(63 downto 0);  
           variable v_OK: boolean;  
      begin  
           tb_ReadEnable <= '0';  
           tb_ReadAddress <=(others =>'0');  
           ---wait for Mul done       
           wait until rising_edge(tb_DataReady);   
           wait until falling_edge(tb_DataReady);   
           READLINE(FI, Lm);  
           Write(L, STRING'("OutputMultC"));  
           WRITELINE(FO, L);  
           tb_ReadEnable<= '1' ;  
           while not ENDFILE(FI) loop  
                wait until rising_edge(tb_Clock);  
                wait for 20 ns;  
                READLINE(FI, Lm);  
                HREAD(Lm, v_ReadDatam);            
                if v_ReadDatam = tb_ReadData then  
                     v_OK :=True;  
                     report "Matched";  
                else  
                     v_OK :=False;  
                end if;  
                HWRITE(L, '0'& tb_ReadData, Left, 10);  
                WRITE(L, v_OK, Right, 10);                 
                WRITELINE(FO, L);  
                tb_ReadAddress <= std_logic_vector(unsigned(tb_ReadAddress)+1);  
           end loop;  
           tb_ReadEnable <= '0';  
           assert false report "Simulation Finished" severity failure; -- to stop simulation  
           wait;   
      end process;  
 end;  

矩阵乘法设计的行为仿真

完成乘法器核心设计后,我们对核心进行行为模拟。这 testbench正在读取输入A和B,然后产生输出C,然后与MATLAB结果进行比较。如果结果与MATLAB相比,结果为100%,则输出文件中的数据“OutputMultC.txt” will be “true”。否则,这将是假的。
矩阵乘法的fun88英超代码
行为模拟波形
在34816个时钟周期之后,完成了具有大小32x32的矩阵的矩阵乘法,并且信号“dataready”被置于高位。它是合理的,因为需要32个周期来计算输出矩阵C的每个矩阵分量。还有2个循环,用于为每个矩阵组件保存数据和将数据写入缓冲器C.因此,存在34个时钟周期来计算矩阵C的一个分量。矩阵C的大小是32×32,然后我们具有矩阵乘法时间为32×32x34 = 34816循环。
与MATLAB相比,行为仿真结果是正确的。实际上,输出文件“OutputMultC.txt” is all “true”。我们还检查内存 缓冲区输出的内容以及结果当然类似于MATLAB计算。
路线后仿真
要执行路线后模拟,我们合成并获取邮政翻译的网格列表进行模拟。合成结果表示该设计的时钟的最大频率为120.757MHz。这意味着时钟的最小时期为8.281ns。因此,32x32矩阵的最小乘法时间为34816x8.281ns = 288.311 US。
路线后仿真结果与MATLAB结果和行为仿真准确相似。实际上,输出文件“OutputMultC.txt” is all “true” as our expectation.

在该项目中,在Xilinx的FPGA Spartan6上实现了具有32x32 16位无符号整数的矩阵的矩阵乘法。 32x32矩阵的最小乘法时间为288.311 US。



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7评论:

  1. 你好!
    我可以用船上的vivado实现这个项目。我试图这样做,但vivado 2015.4没有'读/读取这些文件(InputBuffera - DPRAM1024X16,InputBufferB - DPRAM1024X16和OutputBufferCERC - DPRAM1024X64)
    或者我'll必须创建它们并抛入一个文件夹"sources".
    你能帮助我吗?我会为答案感到高兴。

    回复 删除
  2. 您必须使用Xilinx Generator生成该内存。然后将其包含到项目中。

    回复 删除
  3. 这段代码可以用于FPGA Model De2i - 150

    回复 删除
    答案
    1. 它可能是可能的,但您需要通过Quartus Altera替换Xilinx的块RAM IP。

      删除
  4. 嗨,我收到了读命令的错误。从输入文件。我必须进口任何I / O包吗?

    回复 删除
  5. 请某人提供Inputa,InputB,Outporc和Outporc Matlab文件的容纳

    回复 删除

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